Low capacitance wiring layout and method for making same

ABSTRACT

Integrated circuits having multi-level wiring layouts designed to inhibit the capacitive-resistance effect, and a method for fabricating such integrated circuits, is described. The integrated circuits have at least two planes of wiring adjacent to each other and extending in the same direction. One embodiment may further include a larger than normal insulator material between planes of wiring extending in one direction and at least one plane of wiring extending in a second direction transverse to the first direction. Each of the wiring channels in a wiring plane may be offset relative to a respective wiring channel in the next adjacent wiring plane which extends in the same direction.

FIELD OF THE INVENTION

[0001] The present invention relates generally to integrated circuitfabrication, and more particularly to a wiring layout which allows for arelatively high heat conductivity for a given capacitive-resistanceload.

BACKGROUND

[0002] Multi-level wiring in integrated circuits is well known in theindustry. In the early days of the semiconductor industry, nearly all ofthe resistance and the capacitive load in a circuit were in devices. Asdevices have grown smaller and the wiring cross-sections have beenreduced, the capacitive load of the wiring structure and the lineresistivity have grown to the point that they are the largestcontributors to the total capacitive-resistance load on a device. Today,a major problem in the semiconductor processing industry is thecapacitive-resistance effect in the wiring levels. Efforts to reduce theresistance of the wiring levels and to lower the capacitive loading onthe wiring levels has met with poor results.

[0003] Conventionally, aluminum and aluminum alloys have been used forwiring integrated circuits. Aluminum, however, has a poor conductivitycompared with other metals. Copper has also been used. However, copper,unlike aluminum, cannot be reactively ion etched. To be reactively ionetched, the object being etched must form a volatile compound at roomtemperature, and copper does not do so. Thus, wires, or lines, of coppermust be formed in a damascene process. In the damascene process, a layerof insulating material is first deposited and patterned by reactive ionetching to form trenches. The conductor material, here copper, isdeposited above a liner and adhesion layer within the trenches.Generally, the copper is deposited by either chemical vapor deposition(CVD) or electroplating. Any unwanted copper and liner may be removed bychemical mechanical polishing (CMP).

[0004] As lithographic dimensions decrease, the capacitive-resistanceproblem is increasing. The capacitive-resistance problem is effected bywires located in the same horizontal plane as well as by wiresvertically separated. The capacitive effect of wires within the sameplane is most directly affected by smaller lithographic dimensions. Thehorizontal and vertical capacitive effects can be mitigated to someextent by making the wiring thinner. Thinning the wiring, however,reduces the cross-section of the wiring, thereby increasing itsresistance. Further, the vertical capacitive effect can be mitigated byincreasing the thickness of the insulative material in which the variouswiring layers are deposited. The insulative materials generally usedhave a low coefficient of thermal conductivity, thereby reducing theheat flow to the top surface of the integrated circuit, causing theintegrated circuit to operate at a higher than desired temperature or areduced power level to avoid an overheating problem.

[0005] Another solution to heat generation and dissipation is to makethe wiring wider to increase the conductivity and/or electromigrationresistance of the wiring. This, however, requires additional wiringplanes, which consequently requires additional levels of insulativematerial, thereby reducing the ability to remove heat from theintegrated circuit.

[0006] FIGS. 1-6 are exemplary depictions of conventional multiple levelwiring layouts which have been used in integrated circuit designs. FIGS.1-6 show a portion of an integrated circuit have wiring channels runningin a first direction at a first level interspersed with wiring channelsat a second level running in a second direction perpendicular to thefirst direction. With specific reference to FIGS. 1-2, an integratedcircuit portion 10, which includes a substrate 13, is shown having a topsurface 12, a bottom surface 14, a first side surface 16, a second sidesurface 18, a third side surface 20, and a fourth side surface 22. Afirst plane of wiring 30 and a third plane of wiring 34 extend from thefirst side surface 16 to the third side surface 20. A second plane ofwiring 32 and a fourth plane of wiring 36 extend from the second sidesurface 18 to the fourth side surface 22. Each of the wiring planes 30,32, 34, 36 include one or more wiring channels 38 into which aredeposited conductive wires 40. The wires may be formed of any conductivematerial, and are preferably formed of copper.

[0007] Each of the wiring planes 30, 32, 34, 36 are set within andseparated by an insulator material, such as an intralayer dielectric 42.As shown, the second plane of wiring 32 is positioned between the firstand third planes of wiring 30, 34, while the fourth plane of wiring 36is beneath the third plane of wiring 34. The width of each of the wiringchannels 38 is generally equivalent to the height of the channels 38,and the pitch is, for example, twice as long as either the height or thewidth of the channels 38.

[0008]FIG. 3 illustrates another integrated circuit 100 having analternative wiring layout configuration. The major difference betweenintegrated circuit 100 and integrated circuit 10 is the configuration ofthe wiring channels, and hence the configuration of the wiring itself.Wiring channels 138 have a height twice that of the width of thechannels 138, and hence the wiring 140 has a greater height than width.

[0009]FIG. 4 illustrates another integrated circuit 200 having aplurality of channels 238 into which wiring 240 is deposited. Channels238 have a height to width ratio of four to one.

[0010]FIG. 5 illustrates another integrated circuit 300 having anadditional four planes of wiring beneath the four planes of wiring 30,32, 34, 36. Specifically, beneath the fourth plane of wiring 36 is afifth plane of wiring 331 which extends in a direction parallel to thefirst and third planes of wiring 30, 34, namely from the first sidesurface 16 to the third side surface 20. Beneath the fifth plane ofwiring 331 are a sixth plane 333, a seventh plane 335, and an eighthplane 337. The seventh plane of wiring 335 extends from the first sidesurface 16 to the third side surface 20, while the sixth and eighthplanes of wiring 333, 337 extend from the second side surface 18 to thefourth side surface 22. As with the first four planes of wiring 30, 32,34, 36, the second four planes of wiring 331, 333, 335, 337 areinterspersed such that each plane does not extend in the same directionas adjacent planes.

[0011]FIG. 6 illustrates another integrated circuit 400 which is similarto integrated circuit 300 (FIG. 5). The difference is that each of thewiring channels 38 in a single plane of wiring is offset relative to thenext closest wiring plane extending in the same direction. For example,the wiring channels 38 in the first wiring plane 30 are offset relativeto the channels 38 in the third wiring plane 34. Further, the channels38 in a fifth wiring plane 431 are offset relative to the channels 38 ina seventh wiring plane 435, and channels 38 in a sixth wiring plane 433are offset relative to those in an eighth wiring plane 437.

[0012] The wiring layouts illustrated in FIGS. 1-6 all havecapacitive-resistance effects. The capacitive-resistance effect (RC) ofthe integrated circuit 10 of FIGS. 1-2 can be expressed by the equation

RC=2r{acute over (εε)}₀ L ²(4/p ²+1/T ²)

[0013] where r equals interconnect resistivity, {acute over (ε)}₀ equalspermittivity of free space, {acute over (ε)} equals the dielectricconstant of the insulator material, L is the interconnect length, p isthe interconnect pitch, and T is the interconnect thickness. Theinterconnect resistivity r is a function of the material from which thewire is formed, and cannot be increased as the pitch and/or thethickness of the wire is reduced. It is also assumed that the thicknessof the insulator material between the wiring planes is equal to thethickness of the wiring 40, and the width of the wiring 40 is equal toone half the pitch.

[0014] Reduction and dissipation of heat caused by current flow in thewiring in an integrated circuit is, as noted, an increasingly importantissue. To obtain additional heat conductivity, and thereby remove/reduceheat effects, the wiring can be made thicker. Thicker wires leads,however, to an undesirable increase in capacitance loading and anincrease in the total RC.

[0015] There exists a need for a multi-level wiring layout, and a methodfor making the same, which allows for increased heat dissipation whilemaintaining relatively low capacitive-resistance values.

SUMMARY

[0016] The invention provides an integrated circuit that includes afirst set of two or more adjacent wiring planes extending in a firstdirection, each of the wiring planes having at least one wiring channelinto which is deposited a conductive element. In one aspect, the wiringchannels of adjacent wiring planes are offset from one another.

[0017] The invention also provides a method for fabricating anintegrated circuit having a plurality of wiring planes, each of theplanes including a plurality of wiring channels. The method includesproviding a first layer of insulator material, masking the first layerof insulator material and etching a first plurality of the wiringchannels in a first direction, filling the first plurality of wiringchannels with conductive material, providing a second layer of insulatormaterial adjacent to the first layer of insulator material, providing athird layer of insulator material adjacent to the second layer ofinsulator material, masking the third layer of insulator material andetching a second plurality of the wiring channels in the firstdirection, the second plurality of wiring channels being offset from thefirst plurality of wiring channels, and filling the second plurality ofwiring channels with conductive material.

[0018] These and other advantages and features of the invention will bemore readily understood from the following detailed description which isprovided in connection with the accompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0019]FIG. 1 is a perspective view of a conventional integrated circuitwiring pattern.

[0020]FIG. 2 is a cross-sectional view of the circuit of FIG. 1 takenalong line II-II.

[0021]FIG. 3 is a cross-sectional view of another conventionalintegrated circuit wiring pattern.

[0022]FIG. 4 is a cross-sectional view of another conventionalintegrated circuit wiring pattern.

[0023]FIG. 5 is a cross-sectional view of another conventionalintegrated circuit wiring pattern.

[0024]FIG. 6 is a cross-sectional view of another conventionalintegrated circuit wiring pattern.

[0025]FIG. 7 is a cross-sectional view of an integrated circuit wiringpattern fabricated in accordance with a first exemplary embodiment ofthe invention.

[0026]FIG. 8 is a cross-sectional view of an integrated circuit wiringpattern fabricated in accordance with a second exemplary embodiment ofthe invention.

[0027]FIG. 9 is a cross-sectional view of an integrated circuit wiringpattern fabricated in accordance with a third exemplary embodiment ofthe invention.

[0028]FIG. 10 is a cross-sectional view of an integrated circuit wiringpattern fabricated in accordance with a fourth exemplary embodiment ofthe invention.

[0029] FIGS. 11-30 are schematic views of integrated circuit wiringpatterns fabricated in accordance with additional exemplary embodimentsof the invention.

[0030]FIG. 31 is a flow diagram of the method for forming multi-layerwiring patterns in accordance with exemplary embodiments of theinvention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0031] Referring now to FIG. 7, there is shown a portion of anintegrated circuit 500 in a first exemplary embodiment of the invention.The integrated circuit 500 has an upper surface 12, a lower surface 14,and first through fourth side surfaces 16, 18, 20 (FIG. 1), and 22. Thecircuit 500 has four planes of wiring, namely a first plane of wiring30, a second plane of wiring 532, a third plane of wiring 534 and afourth plane of wiring 36, each positioned within an insulator materiallayer. The first and fourth planes of wiring 30, 36 are similar to andextend in the same direction as the first and fourth planes of wiringillustrated in FIG. 1. The second plane of wiring 532 is immediatelyadjacent and below the first plane of wiring 30. The first and secondplanes of wiring 30, 532, which extend in the same direction, make up afirst set of wiring planes 501. The third plane of wiring 534 extendsperpendicular to the second plane of wiring 532 and is parallel to thefourth plane of wiring 36, and the third and fourth planes 534, 36 makeup a second set of wiring planes 502.

[0032] Wiring channels 238 in each of the planes of wiring have a heightto width ratio of about four to one. Conductive material 240 isdeposited in each wiring channel 238. Further, each of the wiringchannels 238 in one of the wiring planes, e.g. 30, is offset from thewiring channels 238 in the other wiring plane extending in the samedirection by an amount equal to or about one half of the wiring pitch. Afirst insulator material, such as an intralayer dielectric material 541,is positioned between the first and second wiring planes 30, 532 andbetween the third and fourth planes 534, 36. The first insulatormaterial 541 is about one half of the wire pitch. The insulatormaterials 541 can be thinner due to the offset nature of the wiringchannels 238 between wiring planes.

[0033] A thicker second insulator material, such as an intralayerdielectric material 542, is positioned between the second and thirdplanes 532, 534. The thickness of the insulator material 542 is aboutequal to the thickness of the wiring. The insulator material 542 isthicker to reduce the capacitive-resistance effect between the secondplane of wiring 532 and the third plane of wiring 534, which extends ina direction perpendicular to the second plane of wiring 532.

[0034]FIG. 8 illustrates a portion of an integrated circuit 600 havingsix planes of wiring, each including a plurality of wiring channels 38.The first, second and third wiring planes 30, 632, 34 extend in the samedirection and make up a first set of wiring planes 601. The wiringchannels 38 of the second wiring plane 632 are offset relative to thewiring channels 38 of the first and third wiring planes 30, 34 by anamount equal to or about one half of the wire pitch. A first intralayerdielectric material 541 is positioned between the first and secondplanes of wiring 30,632 and the second and third planes of wiring 632,34.

[0035] The integrated circuit 600 further includes a fourth, fifth andsixth wiring planes 36, 631, 633, each extending in the same directionand in a direction perpendicular to the first three planes of wiring 30,632, 34. The fourth, fifth and sixth wiring planes make up a second setof wiring planes 602. As with the first three planes of wiring, anintralayer dielectric material 541 is located between the fourth andfifth planes of wiring 36, 631 and between the fifth and sixth planes ofwiring 631, 633. A thicker second intralayer dielectric material 542 islocated between the third and fourth planes of wiring 34, 36. The wiringchannels 38 of the fifth wiring plane 631 are offset relative to thewiring channels 38 of the fourth and sixth wiring planes 36,633 by anamount equal to or about one half of the wire pitch. The secondintralayer dielectric material 542 inhibits the capacitive-resistanceeffect between the wiring planes extending in a first direction and thewiring planes extending in a second direction perpendicular to the firstdirection.

[0036]FIG. 9 illustrates a portion of an integrated circuit 700 which,like the integrated circuit 600 of FIG. 8, has six planes of wiring. Thedifference between the circuit 600 and the circuit 700 is that thecircuit 700 includes wiring channels 138 which have a height to widthratio of two to one. The first three planes of wiring 30, 732, 34,making up the first set of wiring planes 601, extend in the samedirection and are separated by a first intralayer dielectric material541. The fourth, fifth and sixth planes of wiring 36, 731, 733, makingup the second set of wiring planes 602, extend in the same direction andin a direction perpendicular to the first three planes of wiring 30,732, 34. The first intralayer dielectric material 541 separates thefourth and fifth planes of wiring 36, 731 and the fifth and sixth planesof wiring 731, 733, while a thicker second intralayer dielectricmaterial 542 separates the first three planes of wiring from the secondthree planes of wiring. As with the circuit 600, the wiring channels 138of the second plane of wiring 732 are offset from the wiring channels138 of the first and third wiring planes 30, 34 by an amount equal to orabout one half of the wire pitch, and the wiring channels 138 of thefifth wiring plane 731 are offset from the wiring channels 138 of thefourth and sixth wiring planes 36, 733 by an amount equal to or aboutone half of the wire pitch.

[0037]FIG. 10 illustrates a portion of an integrated circuit 800 witheight planes of wiring, each having a plurality of wiring channels 38with a height to width ratio of one to one. The first four planes ofwiring 30, 832, 34, 836, which make up the first set of wiring planes701, extend in the same direction and in a direction perpendicular tothe next four planes of wiring 831, 833, 835, 837. Each of the firstfour planes of wiring 30, 832, 34, 836 are separated by a firstintralayer dielectric material 541. Each of the second four planes ofwiring 831, 833, 835, 837, which make up a second set of wiring planes702, also are separated by a first intralayer dielectric material 541,and the fourth plane of wiring 836 is separated from the fifth plane ofwiring 831 by a thicker second intralayer dielectric material 542. Thewiring channels 38 of the second and fourth planes of wiring 832, 836are offset from the first and third planes of wiring 30, 34 by an amountequal to or about one half of the wire pitch. The wiring channels 38 ofthe sixth and eighth planes of wiring 833, 837 are offset from the fifthand seventh planes of wiring 831, 835 by an amount equal to or about onehalf of the wire pitch.

[0038] By placing two or more planes of wiring extending in the samedirection as one another, and by offsetting the respective wiringchannels and locating thinner intralayer dielectric materialtherebetween, the capacitive-resistance effect is inhibited while theheat conductivity of the circuit is enhanced. Table 1 below illustratesthe relative capacitive-resistance value and the relative heatconductance value of each of the integrated circuits illustrated inFIGS. 3-10 as compared to the integrated circuit illustrated in FIGS.1-2. Each of the integrated circuits in Table 1 include wiringcomprising copper and insulative material formed of SiLK, made by Dow.TABLE 1 Relative Relative Heat Integrated Number Metal Metal Capacitive-Con- Circuit (FIG. of Metal Thickness Pitch Resistance duct- No) Levels(T) (p) (RC) ivity  10 (FIGS. 1-2 4 1 2 1.0 1.0 100 (FIG. 3) 4 2 2 0.630.71 200 (FIG. 4) 4 4 2 0.53 0.29 300 (FIG. 5) 8 2 4 0.25 0.29 400 (FIG.6) 8 2 4 0.25 0.29 500 (FIG. 7) 4 4 2 0.53 0.5 600 (FIG. 8) 6 1.5 3 0.440.83 700 (FIG. 9) 6 2.66 3 0.28 0.46 800 (FIG. 10) 8 2 4 0.25 0.45

[0039] From the table above, it is shown that the wiring layouts ofFIGS. 7-10 result in a higher heat conductivity for a given amount ofwiring channels 38 while achieving a low capacitive-resistance effectRC. For example, the integrated circuit 200 of FIG. 4 has a relative RCof 0.53 and a relative heat conductance of 0.29, while the integratedcircuit 500 (FIG. 7) has a relative RC of 0.53 and a relative heatconductance of 0.50. Further, integrated circuits 300, 400 each have arelative RC of 0.25 and a relative heat conductance of 0.29, whileintegrated circuit 800 has a relative RC of 0.25 and a relative heatconductance of 0.45.

[0040] Table 2 on the following page includes calculatedcapacitive-resistance effect RC (pico-ΩC²/Nm) and heat conductivity(w/m°K) based upon the equation RC=2r{acute over (εε)}₀L²(4/p²+1/T²).The dielectric used is Dow SiLK The {acute over (ε)} equals 2.65 with aheat conductivity of 0.19 w/m°K. The {acute over (ε)} equals thepermittivity of vacuum (8.85×10⁻¹²). The conductor is copper with aresistivity r of 16.73 nano-ohm meter, and. TABLE 2 Heat IntegratedNumber Metal Metal Capacitive- Conduct- Circuit (FIG. of Metal ThicknessPitch Resistance ivity No Levels (T) (p) RC (w/m° K.)  10 (FIGS. 4 1 20.0157 0.0356 1-2  10 (FIGS. 4 0.1 0.2 1.57 0.356 1-2 100 (FIG. 3) 4 2 20.0099 0.0253 100 (FIG. 3) 4 0.2 0.2 0.99 0.253 200 (FIG. 4) 4 4 20.0083 0.0103 200 (FIG. 4) 4 0.4 0.2 0.83 0.103 300 (FIG. 5) 8 2 40.0039 0.0103 300 (FIG. 5) 8 0.2 0.4 0.39 0.103 400 (FIG. 6) 8 2 40.0039 0.0103 400 (FIG. 6) 8 0.2 0.4 0.39 0.103 500 (FIG. 7) 4 4 20.0083 0.0178 500 (FIG. 7) 4 0.4 0.2 0.83 0.178 600 (FIG. 8) 6 1.5 30.0069 0.0295 600 (FIG. 8) 6 0.15 0.3 0.69 0.295 700 (FIG. 9) 6 2.66 30.0044 0.0164 700 (FIG. 9) 6 0.266 0.3 0.44 0.164 800 (FIG. 8 2 4 0.00390.016 10) 800 (FIG. 8 0.2 0.4 0.39 0.16 10)

[0041] Multi-level integrated circuits, such as, for example, integratedcircuits 500-800, are structured in a way making them particularlysuited for being manufactured with a dual, triple, or quadrupledamascene process, as will be described below.

[0042] Additional wiring layouts which are within the scope of theinvention are illustrated in FIGS. 11-30. The additional wiring layoutshave been simplified merely for ease of illustration. Although thewiring layouts have been shown and described in reference to integratedcircuits, it is to be understood that similar wiring layouts as shown inFIGS. 7-30 may be formed on a larger scale for printed circuit boards.

[0043] FIGS. 11-12 illustrate two examples of five wiring planes laiddown according to the invention. FIG. 11 shows a set 501 of two wiringplanes separated from a set 503 having a single wiring plane by a set502 of two wiring planes. Set 502 extends transverse to the sets 501 and503. FIG. 12 shows a set 601 of three wiring planes extending in adifferent direction than the set 502 of two wiring planes.

[0044] FIGS. 13-14 illustrate two examples of six wiring planes laiddown according to the invention. Specifically, FIG. 13 illustrates theset 501 of two wiring planes and the set 503 having a single wiringplane extending in the same direction. Further, the set 502 of twowiring planes, which is sandwiched by the sets 501, 503, is shownextending in the same direction as a set 504 having a single wiringplane. FIG. 14 shows tie set 501 adjacent to the set 602, which itselfis adjacent to the set 503.

[0045] FIGS. 15-17 illustrate examples of seven wiring planes laid outin accordance with the invention. FIG. 15 shows the set 601 of threewiring planes adjacent to and extending transversely to a set 702 offour wiring planes. FIG. 16 shows a pair of the sets 501 on either sideof the set 502, with the set 504 being adjacent to the lower of the twosets 501. FIG. 17 shows a pair of the sets 501 sandwiching the set 602.

[0046] FIGS. 18-21 illustrate four examples of eight wiring planes laidout according to the invention. FIG. 18 shows a pair of sets 501 and apair of sets 502 interspersed. FIG. 19 shows the set 601 adjacent andabove the set 602 and the sets 503 and 504. FIG. 20 shows the set 601and the set 602 acting as bookends for the sets 504 and 503. FIG. 21shows a pair of the sets 501 sandwiching the set 702.

[0047] FIGS. 22-24 show examples of nine wiring planes laid outaccording to the invention. Specifically, FIG. 22 shows a set 701 offour wiring planes adjacent to a set 802 of five wiring planes. FIG. 23shows the set 601 adjacent to the set 602. Further, the set 503 issandwiched between the set 602 and the set 502. FIG. 24 shows a pair ofsets 501 sandwiching the set 602, with the set 502 adjacent and belowthe lower of the sets 501.

[0048] FIGS. 25-30 show examples of ten wiring planes laid downaccording to the invention. FIG. 25 shows a set 801 of five wiringplanes adjacent to the set 802. FIG. 26 shows the set 601 adjacent tothe set 602, which is adjacent to the set 501, which itself is adjacentto the set 502. FIG. 27 shows a pair of sets 501 sandwiching the set602, and beneath the lower of the sets 501 is the set 502 and the set503. FIG. 28 shows die set 503 adjacent to the set 502. Beneath the set502 is the set 601, the set 602, and a second set 503. FIG. 29 shows theset 501 adjacent to the set 802, which is adjacent to the set 601. FIG.30 shows the set 601 adjacent to the set 602. Further, a pair of thesets 503 sandwich the set 502.

[0049] With reference to FIG. 31, next will be described an exemplarymethod for forming the multi-layer wiring designs illustrated in FIG. 7.As a first step 900, a first insulator material, such as the intralayerdielectric material 36, is provided over the substrate 13. This layer isthen masked and trenches or channels 38 are etched therein. At step 902,a conductive material 40, such as, for example, copper is deposited inthe trenches 38 of the first insulator material 36 and then theremaining masking material is removed. At step 904, a second, thickerinsulator material, such as the intralayer dielectric material 541 and534, is provided. This layer is then masked and trenches 38 are etchedtherein. The trenches 38 in layer 541 are offset from those in material36. A conductive material 40 is deposited in the trenches at step 906. Athird insulator material thicker than the insulator materials 36, 534,541, such as the intralayer dielectric material 542, is applied at step908, and at step 910 a fourth insulator material, such as the intralayerdielectric material 532, is applied, masked, and trenches 38 are etchedtherein. The trenches 38 of the fourth insulator material are filledwith a conductive material 40 at step 912. A fifth insulator material,such as the intralayer dielectric material 30, is applied, masked andtrenches 38 are etched therein at step 914. The trenches 38 in layer 30are offset from the trenches 38 in layer 532. At step 916, a conductivematerial 40 is deposited in the trenches 38. The steps as described withreference to the integrated circuit portion 500 (FIGS. 7, 31) can bemodified and/or expanded upon in order to form the integrated circuitsdescribed herein.

[0050] While the foregoing has described in detail preferred embodimentsknown at the time, it should be readily understood that the invention isnot limited to the disclosed embodiments. Rather, the invention can bemodified to incorporate any number of variations, alterations,substitutions or equivalent arrangements not heretofore described, butwhich are commensurate with the spirit and scope of the invention. Forexample, while the multi-level integrated circuits described hereingenerally have had between four and eight wiring planes, the number ofwiring planes may be less than four or more than eight. Further, whilethe wiring channels 38, 138, 238 are shown with a rectangular profile,it is to be understood that a circular, oval, or other profile is withinthe scope of the invention. Additionally, the number of insulatingmaterial layers and the thicknesses of the insulating materials can varywithin the scope of the invention. For example, while the invention hasbeen shown with separating insulative layers between two adjacentinsulative layers in which conductors are formed, it is possible toremove any separating insulative layers and make the upper insulatinglayer containing conductors thicker. Accordingly, the invention is notto be seen as limited by the foregoing description, but is only limitedby the scope of the appended claims.

[0051] What is claimed as new and desired to be protected by LettersPatent of the United States is:

1. A metallization structure comprising: a first set of two or morewiring planes, the first wiring plane having a first plurality ofparallel wiring channels and the second wiring plane having a secondplurality of parallel wiring channels, said first set including: a firstinsulating material layer provided over a substrate and supporting saidfirst plurality of wiring channels; and a second insulating materiallayer provided over said first insulating material and supporting saidsecond plurality of wiring channels; wherein said first and secondwiring channels extend in a first direction and said first plurality ofwiring channels are offset relative to said second plurality of wiringchannels.
 2. The metallization structure of claim 1, further comprisinga first insulator layer separating said wiring planes of said first set.3. The metallization structure of claim 2, wherein said first insulatorlayer comprises SiLK.
 4. The metallization structure of claim 1, furthercomprising conductor material within said first and second plurality ofparallel wiring channels.
 5. The metallization structure of claim 4,wherein said conductor material comprises copper.
 6. The metallizationstructure of claim 4, further comprising a second set of wiring planesin a plane parallel to said first set of wiring planes, said second setof wiring planes including at least a first wiring plane with wiringchannels extending in a second direction transverse to said firstdirection.
 7. The metallization structure of claim 6, wherein saidsecond direction is perpendicular to said first direction.
 8. Themetallization structure of claim 6, further comprising a secondinsulator layer separating said wiring planes of said first set fromsaid wiring planes of said second set.
 9. The metallization structure ofclaim 8, wherein said second insulator layer is thicker than said firstinsulator layer.
 10. An integrated circuit comprising: a first set oftwo or more wiring planes, the first wiring plane having a firstplurality of parallel wiring channels and the second wiring plane havinga second plurality of parallel wiring channels, said first setincluding: a first insulating material layer provided over a substrateand supporting a plurality of first wiring channels; and a secondinsulating material layer provided over said first insulating materialand supporting a plurality of second wiring channels; wherein said firstand second wiring channels extend in a first direction and said firstplurality of wiring channels are offset relative to said secondplurality of wiring channels.
 11. The integrated circuit of claim 10,further comprising a first insulator layer separating said wiring planesof said first set.
 12. The integrated circuit of claim 11, wherein saidfirst insulator layer comprises SiLK.
 13. The integrated circuit ofclaim 10, further comprising conductor material within said first andsecond plurality of parallel wiring channels.
 14. The integrated circuitof claim 13, wherein said conductor material comprises copper.
 15. Theintegrated circuit of claim 11, further comprising a second set ofwiring planes in a plane parallel to said first set of wiring planes,said second set of wiring planes including at least a first wiring planewith wiring channels extending in a second direction transverse to saidfirst direction.
 16. The integrated circuit of claim 15, wherein saidsecond direction is perpendicular to said first direction.
 17. Theintegrated circuit of claim 15, further comprising a second insulatorlayer separating said wiring planes of said first set from said wiringplanes of said second set.
 18. The integrated circuit of claim 17,wherein said second insulator layer is thicker than said first insulatorlayer.
 19. The integrated circuit of claim 17, wherein said second setof wiring planes includes a plurality of wiring planes, each with aplurality of wiring channels extending in said second direction.
 20. Theintegrated circuit of claim 11, further comprising a second insulatorlayer separating said wiring planes of said first set from said wiringplanes of said second set.
 21. The integrated circuit of claim 20,wherein said second insulator layer is thicker than said first insulatorlayer.
 22. The integrated circuit of claim 20, wherein said second setof wiring planes includes a plurality of wiring planes, each with aplurality of wiring channels extending in said second direction.
 23. Theintegrated circuit of claim 22, wherein said wiring channels of saidfirst wiring plane of said second set are offset from said wiringchannels of said second wiring plane of said second set.
 24. Theintegrated circuit of claim 15, further comprising a third set of wiringplanes having at least one wiring plane with wiring channels extendingin said first direction.
 25. The integrated circuit of claim 24, furthercomprising a second insulator layer separating said wiring planes ofsaid second set from said wiring planes of said third set.
 26. Theintegrated circuit of claim 24, wherein said third set includes aplurality of wiring planes, each having a plurality of wiring channelsextending in said first direction.
 27. The integrated circuit of claim26, wherein the wiring channels of one of the wiring planes of saidthird set are offset relative to the wiring channels of another of thewiring planes of said third set.
 28. The integrated circuit of claim 15,further comprising a third set of wiring planes having at least onewiring plane with wiring channels extending in said first direction anda plurality of additional sets of wiring planes.
 29. The integratedcircuit of claim 28, wherein said plurality of additional sets of wiringplanes comprises a plurality of wiring planes, each with a plurality ofwiring channels extending in either said first or said second direction.30. A method for fabricating an integrated circuit having a plurality ofwiring planes, each said plane including a plurality of wiring channels,said method comprising: providing a first layer of insulator material;providing a first plurality of wires on said first layer of insulatormaterial; providing a second layer of insulator material over said firstlayer of insulator material, said second layer of insulator materialbeing thicker than said first layer of insulator material; and providinga second plurality of wires on said second layer of insulator material,wherein said second plurality of wires extend in the same direction assaid first plurality of wires and are each offset from said firstplurality of wires.
 31. The method of claim 30, wherein said providingof a first plurality of wires includes providing copper wires.
 32. Themethod of claim 30, further comprising: providing a third layer ofinsulator material over said second layer of insulator material;providing a fourth layer of insulator material over said third layer ofinsulator material; and providing a third plurality of said wiringchannels in said fourth layer of insulator material in a seconddirection transverse to said first direction.
 33. The method of claim32, further comprising: providing a fifth layer of insulator materialover said fourth layer of insulator material; and providing a fourthplurality of said wiring channels in in said fifth layer of insulatormaterial in either said first or said second direction.
 34. A method forfabricating an integrated circuit having a plurality of wiring planes,each said plane including a plurality of wiring channels, said methodcomprising: providing a first layer of insulator material; masking saidfirst layer of insulator material and etching a first plurality of saidwiring channels therein in a first direction; filling said firstplurality of wiring channels with conductive material; providing asecond layer of insulator material over said first layer of insulatormaterial, said second layer of insulator material being thicker thansaid first layer of insulator material; masking said second layer ofinsulator material and etching a second plurality of said wiringchannels therein in said first direction; and filling said secondplurality of wiring channels with conductive material, wherein saidsecond plurality of wiring channels are each offset from said firstplurality of wiring channels.
 35. The method of claim 34, wherein saidproviding of a first plurality of wires includes providing copper wires.36. The method of claim 34, further comprising: providing a third layerof insulator material over said second layer of insulator material;providing a fourth layer of insulator material over said third layer ofinsulator material; masking said fourth layer of insulator material andetching a third plurality of said wiring channels therein in a seconddirection transverse to said first direction; and filling said thirdplurality of wiring channels with conductive material.
 37. The method ofclaim 36, further comprising: providing a fifth layer of insulatormaterial over said fourth layer of insulator material; masking saidfifth layer of insulator material and etching a fourth plurality of saidwiring channels in either said first or said second direction; andfilling said fourth plurality of wiring channels with conductivematerial.